1. Technical Field
The present invention relates generally to semiconductor fabrication, and more particularly to preventing undercutting of a stressed layer during formation of a dual stressed layer for performance enhancement of semiconductor devices.
2. Related Art
The application of stresses to field effect transistors (FETs) is known to improve their performance. When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (or n-channel FET (NFET) drive currents) while compressive stress is known to enhance hole mobility (or p-channel FET (PFET) drive currents). One way to apply such stresses to a FET is the use of intrinsically-stressed barrier silicon nitride layers. For example, a tensile-stressed silicon nitride layer may be used to cause tension in an NFET channel while a compressively-stressed silicon nitride layer may be used to cause compression in a PFET channel. Accordingly, a dual stressed barrier layer is necessary to induce the desired stresses in an adjacent NFET and PFET.
In the formation of a dual barrier silicon nitride layers for stress enhancement of NFET/PFET devices, the first deposited layer is deposited and then is removed over the appropriate FET region by patterning and etching. The second layer is then deposited and then removed over the other of the two FET regions by patterning and etching. One challenge relative to this process is undercutting of the first-deposited stressed layer due to isotropical etch of the first-deposited stressed layer. In particular, the undercut is difficult to refill when the second-deposited stressed layer is deposited. As a result, voids are often formed, which can cause shorting in devices during metal contact formation, thus reducing yield of chips per wafer. One way to address this situation is to use an anisotropical etch to etch the first-deposited stressed layer without undercut. However, undesirable additional spacers remain in the areas (e.g., on the spacer side wall of the FET having the second-deposited stressed layer) where the second layer is deposited, which can degrade device performance of the FET having the second-deposited stressed layer. This situation can also cause gap filling among devices and make it difficult to etch via contacts.
In view of the foregoing, there is a need in the art for a solution to prevent undercutting during formation of dual stressed layers.